IOLTS 2007 - Call for Participation

CALL FOR PARTICIPATION

Scope -- Program Overview -- Venue -- Workshop Registration -- Advance Program -- More Information -- Committees

Scope and Purpose

Issues related to on-line testing are increasingly important in modern electronic systems. In particular, the huge complexity of electronic systems has led to growth in reliability needs in several application domains as well as pressure for low cost products. There is a corresponding increasing demand for cost-effective on-line testing techniques. These needs have increased dramatically with the introduction of very deep submicron and nanometer technologies which adversely impact noise margins and process parameters variations and make integrating on-line testing and fault tolerance mandatory in many modern ICs. The International On-Line Testing Symposium (IOLTS) is an established forum for presenting novel ideas and experimental data on these areas. The symposium also emphasizes on-line testing in the continuous operation of large applications such as wired, cellular and satellite telecommunication, as well as in secure chips. The Symposium is sponsored by the IEEE Computer Society Test Technology Technical Council and organized by TIMA Laboratory, University of Athens and University of Piraeus.

Program Overview

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The technical program of IOLTS 2007 consists of different forms and includes the following:

Sunday July 8 – Full-day Tutorial part of the IEEE Computer Society TTTC Test Technology Educational Program (TTEP) 2007: Soft Errors: Technology Trends, System Effects and Production Techniques, by S.Mitra (Stanford University), P.Sanda (IBM), and N.Seifert (Intel).

Monday July 9 and Tuesday July 10 – Keynote Talks by Kris Flautner (Director of Research and Development, ARM), Marc Derbey (President and CEO, iRoC Technologies) and Sanjiv Taneja (Vice President and General Manager of Test Technology (Cadence Design Systems).

Monday July 9 to Wednesday July 11 – High-quality Technical Paper Sessions on a variety of hot research topics such as: Reliability in Nanometer Technologies, NoC Reliability and Fault Tolerance, Secure Systems, Large-Scale Dependability, Radiation Effects, Dependability of Processors, SoCs. Asynchronous Circuits, etc.

Monday July 9 to Wednesday July 11 – Special Sessions on emerging topics such as Fault Tolerance in Future Massively Parallel Multi-Core Chips, Fault-tolerant and Self-Adapting Design for Power, Yield and Reliability Issues Mitigation, SER Trends in 45nm and Beyond, Aging and Wearout Issues and Mitigation Approaches, etc.

The Venue

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Crete is the fifth largest island in the Mediterranean sea and lies at the point where the continents of Europe, Asia and Africa meet. It has been cultivated for thousands of years and has important Minoan, Greek, Roman and Byzantine archaeological sites. The historical aspects combine with the scenic landscapes of mountains, valleys, and sea to make Crete a beautiful and fascinating area with probably the mildest climate in Europe. IOLTS will be held in Creta Maris Resort on the Cretan Sea that combines Aegean architecture and luxurious facilities. It is situated 24km east of Heraklion International Airport and it is close to the fishing village of Hersonissos, a long sweeping bay of sandy beach and crystal clear water.

Social Program

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This year, IOLTS attendees will enjoy an exciting social program consisting of two parts. The first part includes visits to two fascinating attractions: Arolithos, an original traditional Cretan village and the Palace of Knossos, the largest and most spectacular of all the Minoan palatial centres. The second part of the social program is a gala dinner with traditional greek music and dance.

Workshop Registration & Hotel Reservations

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Information on Registration & Hotel reservations for IOLTS '07 are now available. Advance registrations for both can be received until the 11th of June, 2007.

Advance Program

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Sunday -- Monday -- Tuesday -- Wednesday

July 8 , 2007 (Sunday)

9:00 AM - 10:00 AM	Tutorial Registration

9:00 AM - 5:00 PM	Test Technology Educational Program (TTEP) 2007 Full-Day Tutorial
	*Soft Errors: Technology Trends, System Effects and Production Techniques* S.Mitra (Stanford University) P.Sanda (IBM) N.Seifert (Intel)

4:00 PM - 6:00 PM	Symposium Registration

July 9 , 2007 (Monday)

7:30 AM - 9:00 AM	Symposium Registration

9:00 AM - 10:30 AM	Opening Session
9:00 - 9:15	Welcome Message
9:15 - 10:00	Keynote Talk –Soft-errors Phenomenon Impacts on Design For Reliability Technologies Marc Derbey, President and CEO (iRoC Technologies)
10:00 - 10:30	Invited Talk –Accelerating Yield Ramp through Real-Time Testing Sanjiv Taneja, Vice President and General Manager of Test Technology (Cadence)

10:30 AM - 10:40 AM BREAK

10:40 AM - 11:40 AM	Session 1: Reliability Issues in Nanometer Technologies
1.1	Fuse: A Technique to Anticipate Failures in Adders, J.Abella, X.Vera, A.Gonzalez, O.Unsal, O.Ergin (Intel Barcelona Research Center, Barcelona Supercomputing Center and TOBB University of Economics and Technology)
1.2	Design for Resilience to Soft Errors and Variations, M.Zhang, TM Mak, J.Tschanz, K.S.Kim, N.Seifert, D.Lu (Intel)
1.3	Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield, S.Paul, R.S.Chakraborty, S.Bhunia (Case Western Reserve University)

11:40 AM - 12:00 PM COFFEE BREAK

12:00 PM - 1:00 PM	Session 2: Network-on-Chip Reliability and Fault Tolerance
2.1	Essential Fault-Tolerance Metrics for NoC Infrastructures, C.Grecu, L.Anghel, P.Pande, A.Ivanov, R.Saleh (University of British Columbia, TIMA Laboratory and Washington State University)
2.2	Configurable Error Control Scheme for NoC Signal Integrity, D.Rossi, P.Angelini, C.Metra (University of Bologna)
2.3	An Analytical Model for Reliability Evaluation of NoC Architectures, A.Dalirsani, M.Hosseinabady, Z.Navabi (University of Tehran and Northeastern University)

1:00 PM - 2:00 PM LUNCH

2:00 PM - 3:00 PM	Session 3: Secure Systems
3.1	An On-Line Fault Detection Scheme for SBoxes in Secure Circuits, G.Di Natale, M.-L.Flottes, B.Rouzeyre (LIRMM)
3.2	Latchup effect in CMOS IC: a Solution for Crypto-Processors Protection against Fault Injection Attacks?, N.Buard, F.Miller, C.Ruby, R.Gaillard (EADS and INFODUC)
3.3	An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding, C.A.Papachristou, F.Wolff, O.B.Khaleel (Case Western Reserve University)

3:00 PM - 3:10 PM BREAK

3:10 PM - 4:10 PM	Session 4: Large Scale Dependability
4.1	Online Monitoring of FPGA-based Co-Processing Engines Embedded in Dependable Workstations, N.Bartzoudis, K.McDonald-Maier (University of Essex)
4.2	Methodology and Tools Developed for Validation of COTS-based Fault-Tolerant Spacecraft Supercomputers, M.Pignol (CNES)
4.3	Time-Sensitive Control-Flow Checking for Multitask Operating System-Based SoCs, F.Vargas, L.Piccoli, J.Benfica, A.A. de Alecrim Jr., M.Moraes (Catholic University – PUCRS)

4:10 PM - 3:30 PM BREAK

4:30 PM - 5:30 PM	Session 5: Dependability of Processors, SoCs and Asynchronous Circuits
5.1	A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors, M.Portela-Garcia, C.Lopez-Ongil, M.Garcia Valderas, L.Entrena (Universidad Carlos III de Madrid)
5.2	A Hybrid Approach to Fault Detection and Correction in SoCs, P.Bernardi, L.M.Veiras Bolzani, M.Sonza Reorda (Politecnico di Torino)
5.3	Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs, Y.Monnet, M.Renaudin, R.Leveugle (TIMA Laboratory)

5:30 PM - 5:45 PM BREAK

5:45 PM - 6:45 PM	Special Session 1: Aging and Wearout Issues and Mitigation Approaches Organizers: TM Mak (Intel) and Pia Sanda (IBM)
S1.1	Circuit Failure Prediction Enables Robust System Design Resilient to Aging and Wearout, Subhasish Mitra (Stanford University)
S1.2	Infant Mortality -- the lesser known reliability issue, TM Mak (Intel)
S1.3	Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design, Antonis Papanikolaou, Hua Wang, Miguel Miranda, Francky Catthoor (IMEC)

8:00 PM WELCOME RECEPTION

July 10, 2007 (Tuesday)

8:45 AM - 9:30 AM	Keynote Talk
	Blurring the Layers of Abstractions:Time to take a step back? Krisztián Flautner, Director of Research and Development (ARM Ltd)

9:30 AM - 9:40 AM BREAK

9:40 AM - 11:00 AM	Session 6: Radiation Effects
6.1	Spread in Alpha-Particle-Induced Soft-Error Rate of 90-nm Embedded SRAMs, T.Heijmen (NXP Semiconductors)
6.2	Multiple Event Transients Induced by Nuclear Reactions in CMOS Logic Cells, C.Rusu, A.Bougerol, L.Anghel, C.Weulerse, N.Buard, S.Benhammadi, N.Renaud, G.Hubert, F.Wrobel, T.Carriere, R.Gaillard (TIMA Laboratory, EADS, ATMEL, LPES-CRESA, University of Nice-Sophia Antipolis and INFODUC)
6.3	Single Event Effects in 1Gbit 90nm NAND Flash Memories under Operating Conditions, M.Bagatin, G.Cellere, S.Gerardin, A.Paccagnella, A.Visconti, S.Beltrami, M.Maccarrone (Padova University and STMicroelectronics)
6.4	On Derating Soft Error Probability Based on Strength Filtering, A.Sanyal, S.Kundu (University of Massachusetts, Amherst)

11:00 AM - 11:20 AM COFFEE BREAK

10:50 AM - 12:30 PM	Session 7: Signal Integrity and Error Compensation
7.1	Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC Fabrics, P.Pande, A.Ganguly, B.Feero, C.Grecu (Washington State University and University of British Columbia)
7.2	On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits, J.Semião, J.Freijedo, J.J.Rodríguez-Andina, F.Vargas, M.B.Santos, I.C.Teixeira and J.P.Teixeira (IST/INESC-ID Lisboa, University of Algarve, PUCRS and University of Vigo)
7.3	Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized Checksums, M.Nisar, M.Ashouei, A.Chatterjee (Georgia Institute of Technology)

12:30 PM - 1:30 PM LUNCH

1:30 PM - 2:30 PM	Special Session 2 – Panel: SER Trends in 45nm and Beyond
	Organizers: Lorena Anghel (TIMA) and Dimitris Gizopoulos (University of Piraeus) Panelists: Tino Heijmen (NXP) Franz Ruckerbauer (Infineon) Norbert Seifert (Intel) Marc Derbey (iRoC) Lorena Anghel (TIMA)

2:30 PM - 3:30 PM	Session 8: Posters
8.1	Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment, X.Cano, S.Bota, R.Graciani, D.Gascón, A.Herms, A.Comerma, J.Segura, L.Garrido (Universitat de Barcelona and Universitat de les Illes Balears)
8.2	Robustness of circuits under delay-induced faults: test of AES with the PAFI tool, O.Faurax, A.Tria, L.Freund, F.Bancel (Ecole des Mines de St´Etienne, CEA-LETI, STMicroelectronics and Universite de la Mediterranee)
8.3	A systematic approach for Failure Modes and Effects Analysis of System-On-Chips, R.Mariani, G.Boschi (Yogitech)
8.4	Highly Reliable Power Aware Memory Design, C.A.Argyrides, D.K.Pradhan (University of Bristol)
8.5	Accelerating Soft Error Rate Testing through Pattern Selection, A.Sanyal, K.Ganeshpure, S.Kundu (University of Massachusetts at Amherst)
8.6	Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders, S.Pontarelli, L.Sterpone, G.C.Cardarilli, M.Re, M.Sonza Reorda, A.Salsano, M.Violante (Universita di Roma ”Tor Vergata” and Politecnico di Torino)
8.7	Embedding test patterns into Low-Power BIST sequences, I.Voyiatzis (Technological Educational Institute of Athens)
8.8	Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Block Codes, S.Piestrak, F.Monteiro, H.Jaber, A.Dandache (University of Metz)
8.9	Identification of Critical Errors in Imaging Applications, I.Polian, D.Nowroth, B.Becker (Albert-Ludwigs University, Freiburg)
8.10	Soft Error Rates in 65 nm SRAMs – Analysis of new Phenomena, F.X.Ruckerbauer, Georg Georgakos (Infineon)
8.11	Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC, M.Hosseinabady, M.H.Neishaburi, Z.Navabi (University of Tehran), S.Di Carlo, A.Benso, P.Prinetto, G.Di Natale (Politecnico di Torino and LIRMM)
8.12	Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test Set, H.Rahaman, J.Mathew, D.K.Pradhan (University of Bristol)

4:00 PM Social Event (Tour and Gala Dinner)

July 11, 2007 (Wednesday)

9:00 AM - 10:00 AM	Session 9: Fault Tolerance
9.1	Automated Derivation of Application-aware Error Detectors Using Static Analysis, K.Pattabiraman, Z.Kalbarczyk, R.K.Iyer (University of Illinois, Urbana)
9.2	On-Line Self-Healing of Circuits Implemented on Reconfigurable FPGAs, M.G.Gericota, L.F.Lemos, G.R.Alves, J.M.Ferreira (LABORIS/ISEP and FEUP)
9.3	A C-element Latch Scheme with Increased Transient Fault Tolerance, K.T.Gardiner, A.Yakovlev, A.Bystrov (University of Newcastle upon Tyne)

10:00 AM - 10:10 AM BREAK


10:10 AM - 11:10 AM	Session 10: On-Line Testing for Analog, Mixed-Signal, RF and Delay Defect Tolerance
10.1	Novel Process and Temperature-Stable, On-line Solution for Embedded Analog and Mixed-Signal Test, J.Liobe, M.Margala (University of Rochester and University of Massachusetts Lowell)
10.2	Envelop Detection Based Transition Time Supervision for Online Testing of RF MEMS Switches, E.Simeu, S.Mir, H.N.Nguyen, R.Kherreddine (TIMA Laboratory)
10.3	Tolerance to Small Delay Defects by Adaptive Clock Stretching, S.Ghosh, P.Ndai, S.Bhunia, K.Roy (Purdue University and Case Western Reserve University)

11:10 AM - 11:30 AM COFFEE BREAK

11:30 AM - 12:30 PM	Special Session 3: Fault-tolerant and Self-Adapting Design to Mitigate Power, Yield and Reliability Issues in Upcoming Process Nodes Organizer Rob Aitken (ARM)
S3.1	Statistical device variability and its impact on yield and performance, Asen Asenov (University of Glasgow)
S3.2	Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies, Davide Pandini (ST Microelectronics)
S3.3	GRAAL: a fault tolerant architecture for enabling nanometric technologies, Michael Nicolaidis, (TIMA)

12:30 PM - 1:30 PM LUNCH

1:30 PM - 2:30 PM	Special Session 4: Reconfiguration and Fault Tolerance in Future Massively Parallel Multi-Core Chips Organizer: Nacer-Eddine Zergainoh (TIMA)
S4.1	Resilience, Production Yield and Self-Configuration in the Future Massively Defective Nanochips, Jacques Henri Collet and Piotr Zając (LAAS)
S4.2	Surviving to Errors in Multi-Core Environments, Xavier Vera and Jaume Abella, (Intel Barcelona Research Center)
S4.3	Kris Flautner (ARM)

2:30 PM - 2:40 PM BREAK

2:40 PM - 3:40 PM	Session 11: Processor-Based Testing
11.1	An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores, L.Bolzani, E.Sanchez, M.Schillaci, M.Sonza Reorda, G.Squillero (Politecnico di Torino)
11.2	A Functional Self-Test Approach for Peripheral Cores in Processor-based SoCs, A.Apostolakis, M.Psarakis, D.Gizopoulos, A.Paschalis (University of Piraeus and University of Athens)
11.3	A Configurable Modular Test Processor and Scan Controller Architecture, R.Frost, D.Rudolph, C.Galke, R.Kothe, H.T.Vierhaus (Brandenburg University of Technology Cottbus)

3:40 PM - 4:00 PM COFFEE BREAK

4:00 PM - 4:40 PM	Session 12: Self-Checking and Self-Testing
12.1	Design of Embedded m-out-of-n Code Checkers Using Complete Parallel Counters, S.Tarnick (4TECH GmbH)
12.2	LFSR Reseeding with Irreducible Polynomials, S.Udar, D.Kagaris (Southern Illinois University)

4:40 PM - 5:00 PM CLOSING REMARKS

More Information

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Submission Information

Dimitris Gizopoulos
University of Piraeus
Department of Informatics
80 Karaoli & Dimitriou Str.
18534, Piraeus, Greece
Tel: +30 210 4142372
dgizop@unipi.gr

T.M.Mak
Intel
2200 Mission College Blvd
SC12-604, Santa Clara
CA 95051, USA
Tel: +1 408-765-4543
t.m.mak@intel.com

General Information

Antonis Paschalis
University of Athens
Dept. of Informatics & Telecom.
Panepistimiopolis
15784 Athens, Greece
Tel: +30 210 727 5231
paschali@di.uoa.gr

Michael Nicolaidis
TIMA Laboratory
46, av. Felix Viallet
38031 Grenoble
France
Tel: +33 (0) 4 76 57 46 96
Michael.Nicolaidis@imag.fr

Committees

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ORGANIZING COMMITTEE

General Chairs
M. Nicolaidis, TIMA Laboratory
A. Paschalis, U. Athens

Program Chairs
D. Gizopoulos, U.Piraeus
T.M. Mak, Intel

Vice-General Chairs
C. Metra, U. Bologna
Y. Zorian, Virage Logic

Vice-Program Chairs
R. Aitken, ARM
R. Leveugle, TIMA Laboratory

Finance Chair
M. Psarakis, U. Piraeus

Panels Chair
L. Anghel, TIMA Laboratory

Local Chair
N. Kranitis, U. Athens

Publicity Chair
R. Velazco, TIMA Laboratory

Publications Chair
E. Simeu, TIMA Laboratory

Audio Visual Chair
G. Xenoulis, U. Piraeus

ETTTC Liaison
Z. Peng, Linköping U.

PROGRAM COMMITTEE

J. Abraham, U. Texas at Austin
R. Baumann, Texas Instruments
E. Boehl, Robert Bosch GmbH
C. Bolchini, Poli. di Milano
D. Bradley, ARM
A. Bystrov, U. Newcastle
S. Chakravarty, LSI Logic
Y. Crouzet, LAAS
A. Dandache, U. Metz
P. Fouillat, IXL-ENSEIRB
P. Girard, LIRMM
M. Goessel, U. Postdam
T. Haniotakis, U. Southern Illinois
J. Hayes, U. Michigan
T. Heijmen, NXP Semiconductors
S. Hellebrand, U. Paderborn
A. Ivanov, U. Brit. Columbia
R. Iyer, U. Illinois Urbana
H. Konuk, Broadcom
A. Krasniewski, Warsaw U. T.
S. Kundu, U. Mass. Amherst
C. Landrault, LIRMM
Y. Makris, Yale U.
S. Mitra, Standford U.
D. Nikolos, U. Patras
P. Pande, Washington State U.
I. Parulkar, Sun
B. Paul, Toshiba
M. Pflanz, IBM Germany
S. Piestrak, U. Metz
M. Pignol, CNES
D. Pradhan, U. Bristol
P. Prinetto, Poli. di Torino
M. Rebaudengo, Poli. di Torino
K. Roy, Purdue U.
P. Sanda, IBM
J. Segura, U. Illes Balears
J. P. Seifert, U. of Innsbruck
N. Seifert, Intel
M. Sonza Reorda, Poli. di Torino
J. Sosnowski, Warsaw U. T.
L. Sourgen, ST Microelectronics
B. Straube, Fraunhofer IIS/EAS
J. P. Teixeira, IST/INESC-ID
N. Touba, U. Texas
S. Tragoudas, U. Southern Illinois
Y. Tsiatouhas, U. Ioannina
F. Vargas, PUCRS
I. Verbauwhede, K. U. Leuven
M. Violante, Poli. di Torino
A. Wood, Sun
H. J. Wunderlich, U. Stuttgart
M. Zhang, Intel

For more information, visit us on the web at: http://tima.imag.fr/conferences/iolts/

The 13th IEEE International On-Line Testing Symposium (IOLTS'07) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC), and co-organized by the TTTC On-line Testing TAC and the European Group of TTTC, in collaboration with TIMA Laboratory and University of Bologna.